Chip Designers to Consider before Using Any of the Branch Prediction Schemes. 6.0 Conclusions

After we reviewed our simulation results, we realize that the way we set the combined DHT/BHT table size may not have been the optimal. For simplicity, we assumed that the DHT and BHT components had the same number of table entries. We now feel that a the DHT should have more table entries than the BHT. We believe that the prediction rates will remain lower than the DHT-2 alone. The main advantage of the combined DHT-BHT is that in the BHT we can store the target address and thereby reduce the number of wasted cycles on calculating the target address each time. Given enough hardware, all prediction schemes perform roughly the same. Their relative differences are negligible considering standard deviations of approximately 2.5% from the mean of all benchmarks. The notable exceptions are TLA-6 and TLA-12 whose standard deviation are about 6%. Our most surprising result is that DHT-2 has roughly 90% prediction accuracies for buffer sizes in the 32-64 byte regions. Due to the high accuracy of the small DHT-2, we believe researchers should focus on small and simple branch prediction schemes. However, as is evident in the literature, researchers have been recently looking at increasingly complex branch prediction techniques. Our results demonstrate that these schemes do not improve prediction significantly and perform much worse for low hardware-cost implementations. Correlation based schemes overcome one level techniques only after they reach their saturation point. Because of the low hardware-cost implementations possible with DHT, processor designers should investigate into designing prediction units per process rather than per processor. We have not studied the effect of interleaving instruction streams through a branch prediction simulation and further study in this area is warranted. If target addresses are needed to reduce branch cycle penalties, we recommend combining a DHT-2 with a cache. The cache would store only taken branches using the branch instruction address as a tag and storing the associated target address. This is similar to the combined DHT/BHT proposed in [1] except that it is less complex. Again, in this case, multiple small DHT tables could be introduced to allow for multiple processes.